Analysis and Simulation of the capture process of

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Analysis and Simulation of the capture process of PLL frequency synthesizer

1 overview

PLL is a phase negative feedback technology. PLL circuit is widely used in electronic systems because of its own characteristics:

(1) PLL has no residual frequency difference when locking

(2) PLL has good narrow-band carrier tracking performance

(3) PLL has good broadband modulation tracking performance

(4) good threshold performance

(5) PLL circuits are easy to integrate, and a large number of integrated PLL circuits have come out, which provides convenience for selecting according to different requirements in application

An important application of phase-locked loop circuit is frequency synthesis. Adding a frequency divider between phase detector (PD) and voltage controlled oscillator (VCO) becomes a simple frequency synthesizer. A large number of discrete frequency signals with the same accuracy and stability as the reference frequency source can be generated by the frequency synthesizer. Because of these characteristics, frequency synthesizer has been widely used in modern transceiver

The main performance indicators of the frequency synthesizer are as follows:

(1) frequency range

that is, the frequency band width between the highest and lowest output frequencies of the frequency synthesizer. Generally speaking, the frequency range depends on the frequency variable range of VCO, gene therapy and Biological Nanotechnology

(2) frequency interval

refers to the interval between two adjacent output frequency points of the frequency synthesizer. The frequency range and frequency interval jointly determine the number of channels

(3) conversion time

refers to the time required to complete the conversion and reach the locking when the frequency value changes

(4) noise

characterizes the frequency purity of the output signal. Including phase noise and parasitic interference

among the above performance indicators, the conversion time will greatly affect the effectiveness of communication transmission in the design of transceiver. Every time the transmission and reception frequency changes, it will go through a tracking and locking process of frequency synthesis. When the frequency conversion interval is large, it may take more time. This process cannot carry out effective data transmission, thus reducing the effective channel capacity. In the design of phase-locked frequency synthesizer, minimizing the capture time is an important topic

in this article, the relevant factors of capture time are analyzed, the capture time of a specific PLL circuit is quantitatively analyzed, and the capture process is simulated and described

2 principle of PLL frequency synthesizer

the block diagram of a basic PLL frequency synthesizer is shown in Figure 1 (a). Its basic composition includes four parts: phase detector (PD) and loop filter. The function of PD is to compare the phase of the reference input with the output phase of the voltage controlled oscillator to produce a corresponding comparison. Various qualifications are up to you to consult and inquire, Then, the high-frequency component and noise of the comparison voltage are further filtered through the loop filter to obtain an average value of the voltage, control the output frequency of the VCO, and finally stabilize the output frequency of the VCO at the required value

Figure 1 (b) is the corresponding mathematical model. among φ R (s) is the input reference phase, φ E (s) is the reference phase φ R (s) and VCO output phase φ O (s) phase obtained after N frequency division φ Phase difference of I (s). KPD and GlpF (s) are the transfer functions of phase detector, loop filter and voltage controlled oscillator respectively, and H (s) is the feedback transfer function

the PLL open-loop transfer function is:

from the closed-loop transfer function, it can be found that the order of the PLL is at least one order, and is closely related to the order of the loop filter. They have such a relationship that the order of the PLL is always one order higher than that of the loop filter, that is, the PLL composed of the first-order loop filter is second-order, the PLL composed of the second-order loop filter is third-order, and the order of the loop filter determines the order of the PLL

in modern communication systems, in order to achieve higher performance indicators, most of them are second-order systems that are higher than and enable them to deliver longer distances safely and quickly. It is a common phenomenon to use second-order or third-order loop filters. Using a high-order loop filter can shorten the capture time and improve the suppression of phase noise and parasitic interference

the problem brought by the high-order loop filter is that the theoretical analysis of the phase-locked loop becomes very complex. In this article, the analysis process of the system composed of the third-order loop filter is provided, and the response equation and the method of obtaining the capture time through simulation are given

3 analysis process Max phase is called a ductile and machinable ceramic structure and simulation results

Figure 2 is the circuit diagram of a specific third-order loop filter. The following is a detailed analysis process through this example

in order to simplify the function equation, define the parameters:

the transfer function of the third-order loop filter can be written as:

analyze this closed-loop transfer function. First, it is very difficult to calculate manually by requiring the four zeros of the denominator. Now we can achieve this goal with the help of computers. Such a function is provided in MATLAB software, and we can easily get its zero

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